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91400 rm (im) sk no.6717-1/23 ver.1.04 12000 preliminary overview the LC876596B and lc876580b are 8 bit single chip microcontrollers with the following on-chip functional blocks : - cpu: operable at a minimum bus cycle time of 100 ns - on-chip rom maximum capacity : LC876596B 96k bytes lc876580b 80k bytes - on-chip ram: 2048 bytes - vfd automatic display controller / driver - 16 bit timer / counter (can be divided into two 8 bit timers) - 16 bit timer / pwm (can be divided into two 8 bit timers) - timer for use as date / time clock - synchronous serial i/o port (with automatic block transmit / receive function) - asynchronous / synchronous serial i/o port - 12-channel 8-bit ad converter - weak signal detector - 15-source 10-vectored interrupt system all of the above functions are fabricated on a single chip. features (1) read-only memory (rom): LC876596B 98304 8 bits lc876580b 81920 8 bits (2) random access memory (ram): LC876596B/80b 2048 9 bits (3) minimum bus cycle time: 100 ns (10 mhz) note: the bus cycle time indicates rom read time. 8-bit single chip microcontroller with 96/80 kb rom and 2048-byte ram on chip LC876596B/80b ordering number : enn*6717 cmos ic
LC876596B/80b no.6717-2/23 (4) minimum instruction cycle time: 300 ns (10mhz) (5) ports - input/output ports data direction programmable for each bit individually : 20 (p1n, p70 to p73, p8n) - 15v withstand input/output ports data direction programmable in nibble units : 8 (p0n) (when n-channel open drain output is selected, data can be input in bit units.) data direction programmable for each bit individually : 8 (p3n) - input ports : 2 (xt1,xt2) - vfd output ports large current outputs for digits : 9 (s0 / t0 to s8 / t8) large current outputs for digits / segments : 7 (s9 / t9 to s15 / t15) digit / segment outputs : 8 (s16 to s23) segment outputs : 28 (s24 to s51) other functions input/output ports : 12(pfn, pg0 to 3) input ports : 24 (pcn, pdn, pen) - oscillator pins : 2 (cf1,cf2) - reset pin : 1 (res#) - power supply : 6 (vss1 to 2, vdd1 to 4) - vfd power supply : 1 (vp) (6) vfd automatic display controller - programmable segment/digit output pattern output can be switched between digit/segment waveform output (pins 9 to 24 can be used for output of digit waveforms. parallel-drive available for large current vfd. - 16-step dimmer function available (7) weak signal detection (mic signals etc) - counts pulses with width greater than a preset value - 2 bit counter (8) timers - timer 0: 16 bit timer / counter with capture register mode 0: 2 channel 8-bit timer with programmable 8 bit prescaler and 8 bit capture register mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit counter with 8-bit capture register mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register mode 3: 16 bit counter with 16 bit capture register - timer 1: pwm / 16 bit timer toggle output mode 0: 2 channel 8 bit timer (with toggle output) mode 1: 2 channel 8 bit pwm mode 2: 16 bit timer (with toggle output) toggle output also possible using lower order 8 bits. mode 3: 16 bit timer (with toggle output) lower order 8 bits can be used as pwm output. - base timer 1) the clock signal can be selected from any of the following : sub-clock (32.768khz crystal oscillator), system clock, and prescaler output from timer 0 2) interrupts can be selected to occur at one of five different times.
LC876596B/80b no.6717-3/23 (9) serial-interface - sio 0: 8 bit synchronous serial interface 1) lsb first / msb first function available 2) internal 8 bit baud-rate generator (maximum transmit clock period 4 / 3 tcyc) 3) continuous automatic data communication (1-256 bits) - sio 1: 8 bit asynchronous / synchronous serial interface mode 0: synchronous 8 bit serial io (2-wire or 3-wire, transmit clock 2?512 tcyc) mode 1: asynchronous serial io (half duplex, 8 data bits, 1 stop bit, baud rate 8?2048tcyc) mode 2: bus mode 1 (start bit, 8 data bits, transmit clock 2?512 tcyc) mode 3: bus mode 2 (start detection, 8 data bits, stop detection) (10) ad converter -8 bits 12 channels (11) remote control receiver circuit (connected to p73 / int3 / t0in terminal) -noise rejection function (noise rejection filter time constant can selected from 1 / 32 / 128 tcyc) (12) watchdog timer - the watching timer period is set using an external rc. - watchdog timer can produce interrupt, system reset (13) interrupts: 15-source, 10-vectored interrupts 1) three priority (low, high and highest) multiple interrupts are supported. during interrupt handling, an equal or lower priority interrupt request is refused. 2) if interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence. in the case of equal priority levels, the vector with the lowest address takes precedence. (14) subroutine stack levels: 1024 levels max. stack is located in ram. (15) multiplication and division - 16 bit 8 bit (executed in 5 cycles) - 24 bit 16 bit (12 cycles) - 16 bit 8 bit (8 cycles) - 24 bit 16 bit (12 cycles) (16) oscillation circuits - on-chip rc oscillation circuit for system clock use. - on-chip cf oscillation circuit for system clock use. (r f built in) - on-chip crystal oscillation circuit low speed system clock use. (rd, r f external) (17) standby function - halt mode halt mode is used to reduce power consumption. program execution is stopped. peripheral circuits still operate but vfd display and some serial transfer operations stop. 1) oscillation circuits are not stopped automatically. 2) release occurs on system reset or by interrupt. -hold mode hold mode is used to reduce power consumption. both program execution and peripheral circuits are stopped. 1) cf, rcand crystal oscillation circuits stop automatically. 2) release occurs on any of the following conditions. (1) input to the reset pin goes low (2) a specified level is input at least one of int0, int1, int2 (3) an interrupt condition arises at port 0
LC876596B/80b no.6717-4/23 -x?tal hold made x?tal hold mode is used to reduce power consumption. program execution is stopped. all peripheral circuits except the base timer are stopped. 1) cf and rc oscillation circuits stop automatically. 2) crystal oscillator is maintained in its state at hold mode inception. 3) release occurs on any an any of the following conditions (1) input to the reset pin goes low (2) a specified level is input to at least one of int0, int1, int2 (3) an interrupt condition arises at port 0 (4) an interrupt condition arises at the base-timer (18) factory shipment -delivery form qip100e (19) development tools - evaluation chip: lc876096 - emulator: eva62s + ecb876500 (evaluation chip board) + sub876500 + pod100qfp - flash rom version: lc87f65c8a
LC876596B/80b no.6717-5/23 pin assignment sanyo : qip-100e ver.1.00 package dimension (unit : mm) 3151 sanyo : qip-100e s19/pc3 s18/pc2 s17/pc1 s16/pc0 vdd3 s15/t15 s14/t14 s13/t13 s12/t12 s11/t11 s10/t10 s9/t9 s8/t8 s7/t7 s6/t6 s5/t5 s4/t4 s3/t3 s2/t2 s1/t1 s48/pg0 s49/pg1 s50/pg2 s51/pg3 p00 p01 p02 p03 vss2 vdd2 p04 p05 p06 p07 p10/so0 p11/si0/sb0 p12/sck0 p13/so1 p14/si1/sb1 p15/sck1 s47/pf7 s46/pf6 s45/pf5 s44/pf4 s43/pf3 s42/pf2 s41/pf1 s40/pf0 vdd4 s39/pe7 s38/pe6 s37/pe5 s36/pe4 s35/pe3 s34/pe2 s33/pe1 s32/pe0 s31/pd7 s30/pd6 s29/pd5 s28/pd4 s27/pd3 s26/pd2 s25/pd1 s24/pd0 s23/pc7 s22/pc6 s21/pc5 s20/pc4 vp p16/t1pwm l p17/t1pwmh/bu z p30 p31 p32 p33 p34 p35 p36 p37 res xt1/an10 xt2/an11 vss1 cf1 cf2 vdd1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7/mici n p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0i n p73/int3/t0i n s0/t0 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
LC876596B/80b no.6717-6/23 system block diagram interrupt control stand-by control ir pla rom clock generator cf rc x?tal pc bus interface port 0 port 1 sio0 sio1 timer 0 timer 1 base timer vfd controller int0 - 3 noise rejection filter port 3 port 7 port 8 adc weak signa detector acc b register c register psw rar ram stack pointer watch dog timer alu
LC876596B/80b no.6717-7/23 pin assignment pin name i/o function option vss1 vss2 - power supply (-) no vdd1 vdd2 vdd3 vdd4 - power supply (+) no vp - power supply (-) no port0 p00 to p07 i/o 8bit input/output port data direction programmable in nibble units use of pull-up resistor can be specified in nibble units input for hold release input for port 0 interrupt 15v withstand at n-channel open drain output ye s port1 p10 to p17 i/o 8bit input/output port data direction programmable for each bit use of pull-up resistor can be specified for each bit other pin functions p10 sio0 data output p11 sio0 data input/bus input/output p12 sio0 clock input/output p13 sio1 data output p14 sio1 data input/bus input/output p15 sio1 clock input/output p16: timer 1 pwml output p17: timer 1 pwmh output/buzzer output ye s port3 p30 to p33 i/o 8bit input/output port data direction can be specified for each bit use of pull-up resistor can be specified for each bit 15v withstand at n-channel open drain output ye s 4bit input/output port data direction can be specified for each bit use of pull-up resistor can be specified for each bit other functions p70: int0 input/hold release input/timer0l capture input/output for watchdog timer p71: int1 input/hold release input/timer0h capture input p72: int2 input/hold release input/timer 0 event input/timer0l capture input p73: int3 input(noise rejection filter attached input)/timer 0 event input/timer0h capture input ad input port: an8(p70), an9(p71) the following types of interrupt detection are possible: rising falling rising/ falling h level l level int0 int1 int2 int3 ye s ye s ye s ye s ye s ye s ye s ye s no no ye s ye s ye s ye s no no ye s ye s no no port7 p70 to p73 i/o no
LC876596B/80b no.6717-8/23 pin name i/o function description option port8 p80 to p87 i/o 8bit input/output port input/output can be specified in a bit unit other functions: ad input port: an0 to an7 weak signal detector input port: micin(p87) no s0/t0 to s6/t6 o large current output for vfd display controller digit (can be used for segment) yes s7/t7 to s8/t8 o large current output for vfd display controller digit (can be used for segment) no s9/t9 to s15/t15 o large current output for vfd display controller segment/digit no s16 to s23 i/o output for vfd display controller segment/digit other functions: high voltage input port: pc0 to pc7 no s24 to s31 i/o output for vfd display controller segment other functions: high voltage input port: pd0 to pd7 no s32 to s39 i/o output for vfd display controller segment other functions high voltage input port: pe0 to pe7 ye s s40 to s47 i/o output for vfd display controller segment other functions: high voltage input/output port: pf0 to pf7 ye s s48 to s51 i/o output for vfd display controller segment other functions: high voltage input/output port: pg0 to pg3 no res i reset terminal no xt1 i input for 32.768khz crystal oscillation other functions: general purpose input port when not in use, connect to vdd1. ad input port: an10 no xt2 i/o output for 32.768khz crystal oscillation other functions: general purpose input port when not in use, set to oscillation mode and leave open circuit. ad input port: an11 no cf1 i input terminal for ceramic oscillator no cf2 o output terminal for ceramic oscillator no
LC876596B/80b no.6717-9/23 port output configuration output configuration and pull-up/pull-down resistor options are shown in the following table. input /output is possible even when port is set to output mode. terminal option applies to: options output format pull-up resistor pull-down resistor 1 cmos programmable (note 1) - p00 to p07 1 bit units 2 15 voltage nch-open drain none - 1 cmos programmable - p10 to p17 each bit 2 nch-open drain programmable - 1 cmos programmable - p30 to p37 each bit 2 15v nch-open drain none - p70 - none nch-open drain programmable - p71 to p73 - none cmos programmable - p80 to p87 - none nch-open drain none - 1 high voltage pch-open drain - fixed s0/t0 to s6/t6 each bit 2 high voltage pch-open drain - none s7/t7 to s15/t15 s16 to s31 - none high voltage pch-open drain - fixed 1 high voltage pch-open drain - fixed s32 to s47 each bit 2 high voltage pch-open drain - none s48 to s51 - none high voltage pch-open drain - none xt1 - none input only none - xt2 - none output for 32.768khz crystal oscillation none - note 1 programmable pull-up resisters of port 0 can be attatched in nibble units (p00-03, p04-07). * note 1: connect as follows to reduce noise on vdd and increase the back-up time. vss1, and vss2 must be connected together and grounded. *note 2 : the power supply for the internal memory is vdd1 but it uses the vdd2 as the power supply for ports. when the vdd2 is not backed up, the port level does not become ?h? even if the port latch is in the ?h? level. therefore, when the vdd2 is not backed up and the port latch is ?h? level, the port level is unstable in the hold mode, and the back up time becomes shorter because the through current runs from vdd to gnd in the input buffer. if vdd2 is not backed up, output ?l? by the program or pull the port to ?l? by the external circuit in the hold mode so that the port level becomes ?l? level and unnecessary current consumption is prevented. lsi vdd1 back-up capacitors *2 vdd2 vdd3 vss2 vss1 vdd4 power supply vfd powers
LC876596B/80b no.6717-10/23 1. absolute maximum ratings at ta=25 c and vss1=vss2=0v ratings parameter symbol pins conditions vdd [v] min. typ. max. unit supply voltage vddmax vdd1,vdd2, vdd3,vdd4 vdd1=vdd2=vdd 3=vdd4 -0.3 +7.0 vi(1) xt1,xt2,cf1, res -0.3 vdd+0.3 input voltage vi(2) vp vdd-45 vdd+0.3 output voltage vo(1) s0/t0 to s15/t15 vdd-45 vdd+0.3 vio(1) port 0: cmos output option port 1 port 3: cmos output option port 7 port 8 -0.3 vdd+0.3 vio(2) port 0 open drain port 3 open drain -0.3 15 input/output voltage vio(3) s16 to s51 vdd-45 vdd+0.3 v ioph(1) port 0, 1, 3 cmos output selected current at each pin -10 ioph(2) port71,72,73 current at each pin -3 ioph(3) s0/t0 to s15/t15 current at each pin -30 peak output current ioph(4) s16 to s51 current at each pin -15 ioah(1) port 0 total of all pins -30 ioah(2) port 1,3 total of all pins -30 ioah(3) port 7 total of all pins -5 ioah(4) s0/t0 to s15/t15 total of all pins -65 ioah(5) s16 to s27 total of all pins -60 ioah(6) s28 to s39 total of all pins -60 high level output current total output current ioah(7) s40 to s51 total of all pins -60 iopl(1) port 02, 03 for each pin 30 iopl(2) port 00,01,04 to 07 port 1,3 for each pin 20 peak output current iopl(3) port 7,8 for each pin 5 ioal(1) port 0 for each pin 60 low level output current total output current ioal(2) ports 1,3 for each pin 50 ioal(3) ports 7,8 for each pin 20 ma maximum power dissipation pdmax qip100e ta = -30 to +70 c 500 mw operating temperature range topr -30 70 storage temperature range tstg -55 125 c
LC876596B/80b no.6717-11/23 2. recommended operating range at ta=-30 c to +70 c, vss1=vss2=0v ratings parameter symbol pins conditions vdd [v] min. typ. max. unit operating supply voltage range vdd(1) vdd1=vdd2= vdd3=vdd4 0.294 s t cyc 200 s 4.5 6.0 hold voltage vhd vdd1 ram and the register data are kept in hold mode. 2.0 6.0 pull-down voltage vp vp 4.5?6.0 -35 vdd vih(1) port 0,3: cmos output option port 8 output disable 4.5?6.0 0.3vdd +0.7 vdd vih(2) port 0,3: n-ch open drain output output disable 4.5?6.0 0.3vdd +0.7 13.5 vih(3) port 1 port71,72,73 p70 port input/interrupt output disable 4.5?6.0 0.3vdd +0.7 vdd vih(4) s16 to s51 output p-channel tr. off 4.5?6.0 0.3vdd +1.0 vdd vih(5) p70 weak signal input output disable 4.5?6.0 0.75vdd vdd vih(6) port 70 watchdog timer output disable 4.5?6.0 0.9vdd vdd input high voltage vih(7) xt1, xt2, cf1, res 4.5?6.0 0.75vdd vdd vil(1) port 0,3: cmos output option port 8 output disable 4.5?6.0 vss 0.15vdd +0.4 vil(2) port 0,3: n-ch open drain output output disable 4.5?6.0 vss 0.15vdd +0.4 vil(3) port 1 port 71,72,73 p70 port input/interrupt output disable 4.5?6.0 vss 0.1vdd +0.4 vil(4) s16 to s51 output p-channel tr. off 4.5?6.0 -35 0.2vdd vil(5) port 87 weak signal input output disabled 4.5?6.0 vss 0.25vdd vil(6) port 70 watchdog timer output disabled 4.5?6.0 vss 0.8vdd -1.0 input low voltage vil(7) xt1,xt2,cf1, res 4.5?6.0 vss 0.25vdd v operation cycle time t cyc 4.5?6.0 0.294 200 s cf2 open circuit system clock divider set to 1/1 external clock duty = 5050% 4.5?6.0 0.1 10 mhz external system clock frequency fexcf(1) cf1 cf2 open circuit system clock divider set to 1/2 4.5?6.0 0.2 20 continued/
LC876596B/80b no.6717-12/23 ratings parameter symbol pins conditions vdd[v] min. typ. max. unit fmcf(1) cf1, cf2 10mhz ceramic resonator oscillation refer to figure 1 4.5?6.0 10 fmcf(2) cf1, cf2 4mhz ceramic resonator oscillation refer to figure 1 4.5?6.0 4 fmrc rc oscillation 4.5?6.0 0.3 1.0 2.0 oscillation stabilizing time period (note 1) fsx?tal xt1, xt2 32.768khz crystal resonator oscillation refer to figure 2 4.5?6.0 32.768 (note 1) the oscillation constant is shown in table 1 and table 2.
LC876596B/80b no.6717-13/23 3. electrical characteristics at ta=-30 c to +70 c, vss1=vss2=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iih(1) ports 0,3: n-ch open drain output output disabled vin=13.5v (including off state leak current of the output tr.) 4.5?6.0 5 iih(2) port 0,1,3,7,8 output disabled pull-up resister off. vin=vdd (including off state leak current of the output tr.) 4.5?6.0 1 iih(3) s16 to s51 without pull-down resister (port c,d,e,f,g) when configured as an input port vin=vdd 4.5?6.0 60 iih(4) res vin=vdd 4.5?6.0 1 iih(5) xt1,xt2 when configured as an input port vin=vdd 4.5?6.0 1 iih(6) cf1 vin=vdd 4.5?6.0 15 input high current iih(7) p87/an7/micin weak signal input vin=vbis+0.5v (vbis : bias voltage) 4.5?6.0 4.2 8.5 15 iil(1) port 0,1,3,7,8 output disabled vin=vss (including off state leak current of the output tr.) 4.5?6.0 -1 iil(2) res vin=vss 4.5?6.0 -1 iil(3) xt1,xt2 when configured as an input port vin=vss 4.5?6.0 -1 iil(4) cf1 vin=vss 4.5?6.0 -15 input low current iil(5) p87/an7/micin weak signal input vin=vbis-0.5v (vbis : bias voltage) 4.5?6.0 -15 -8.5 -4.2 a voh(1) ioh=-1.0ma 4.5?6.0 vdd-1 voh(2) port 0,1,3: cmos output option ioh=-0.1ma 4.5?6.0 vdd-0.5 voh(3) port 7 ioh=-0.4ma 4.5?6.0 vdd-1 voh(4) ioh=-20.0ma 4.5?6.0 vdd-1.8 voh(5) s0/t0?s15/t15 ioh=-1.0ma ioh at any single pin is not over 1ma. 4.5?6.0 vdd-1 voh(6) ioh=-5.0ma 4.5?6.0 vdd-1.8 output high voltage voh(7) s2+ to s51 ioh=-1.0ma ioh at any single pin is not over 1ma. 4.5?6.0 vdd-1 vol(1) port 02, 03 iol=30ma 4.5?6.0 1.5 vol(2) iol=10ma 4.5?6.0 1.5 output low voltage vol(3) port 0,1,3 iol=1.6ma 4.5?6.0 0.4 v pull-up resistor rpu port 0,1,3,7 voh=0.9vdd 4.5?6.0 15 40 0 k ? continued/
LC876596B/80b no.6717-14/23 ratings parameter symbol pins conditions vdd[v] min. typ. max. unit ioff(1) output p-ch tr. off vout=vss 4.5?6.0 -1 output off- leak current ioff(2) s0/t0 to s15/t15, s16 to s51 without pull-down resistor output p-ch tr. off vout=vdd-40v 4.5?6.0 -30 a resistance of the low level hold tr. rinpd s16 to s51 output p-ch tr. off 4.5?6.0 200 high voltage pull-down resistor rpd s0/t0 to s15/t15, s16 to s51 with pull-down resistor output p-ch tr. off vout=3v vp=-30v 5.0 60 100 200 k ? vhis(1) port 1,7 res 4.5?6.0 0.1vdd hysteresis voltage vhis(2) port 87 weak signal input 4.5?6.0 0.1vdd v pin capacitance cp all pins all other terminals connected to vss. f =1mhz t a =25 c 4.5?6.0 10 pf input sensitivity vsen port 87 weak signal input 4.5?6.0 0.12vdd vpp
LC876596B/80b no.6717-15/23 4. serial input/output characteristics at ta=-30 c to +70 c, vss1=vss2=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit cycle time tsck(1) 4/3 tsckl(1) 2/3 low level pulse width tsckla(1) 2/3 tsckh(1) 2/3 high level pulse width tsckha(1) sck0(p12) refer to figure 6 4.5?6.0 3 cycle time tsck(2) 2 low level pulse width tsckl(2) 1 input clock high level pulse width tsckh(2) sck1(p15) refer to figure 6 4.5?6.0 1 cycle time tsck(3) 4/3 t cyc tsckl(3) 1/2 low level pulse width tsckla(2) 3/4 tsckh(3) 1/2 high level pulse width tsckha(2) sck0(p12) cmos output option refer to figure 6 4.5?6.0 2 tsck cycle time tsck(4) 2 tcyc low level pulse width tsckl(4) 1/2 serial clock output clock high level pulse width tsckh(4) sck1(p15) cmos output option refer to figure 6 4.5?6.0 1/2 tsck data set-up time t sdi 0.03 serial input data hold time t hdi si0(p10), si1(p13), sb0(p11), sb1(p14) measured with respect to si0clk leading edge. refer to figure 6 4.5?6.0 0.03 serial output output delay time tddo so0(p12), so1(p15), sb0(011), sb1(p14) measured with respect to si0clk trailing edge. when port is open drain: time delay from si0clk trailing edge to the so data change. refer to figure 6 4.5?6.0 1/3 tcyc +0.05 s
LC876596B/80b no.6717-16/23 5. pulse input conditions at ta=-30 c to +70 c, vss1=vss2=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit tpih(1) tpil(1) int0(p70), int1(p71), int2(p72) interrupt acceptable events to timer 0 can be input. 4.5?6.0 1 tpih(2) tpil(2) int3(p73) (noise rejection ratio set to 1/1.) interrupt acceptable events to timer 0 can be input. 4.5?6.0 2 tpih(3) tpil(3) int3(p73) (noise rejection ratio set to 1/32.) interrupt acceptable events to timer 0 can be input. 4.5?6.0 64 tpih(4) tpil(4) int3(p73) (noise rejection ratio set to 1/128.) interrupt acceptable events to timer 0 can be input. 4.5?6.0 256 tpil(5) tpil(5) micin(p87) weak signal detection counter enabled 4.5?6.0 1 t cyc high/low level pulse width tpil(6) res# reset possible 4.5?6.0 200 s 6. ad converter characteristics at ta=-30 c to + 70 c, vss1=vss2=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit resolution n 4.5?6.0 8 bit absolute precision et (note2) 4.5?6.0 1.5 lsb ad conversion time = 32 tcyc (adcr2=0) (note 3) 15.62 (tcyc= 0.488 s) 97.92 (tcyc= 3.06 s) conversion time tcad ad conversion time = 64 tcyc (adcr2=1) (note 3) 4.5?6.0 18.82 (tcyc= 0.294 s) 97.92 (tcyc= 1.53 s) s analog input voltage range vain 4.5?6.0 vss vdd v iainh vain=vdd 4.5?6.0 1 a analog port input current iainl an0(p80) to an7(p87) an8(p70), an9(p71) an10(xt1), an11(xt2) vain=vss 4.5?6.0 -1 (note 2) absolute precision not including quantizing error (1/2 lsb). (note 3) conversion time means time from executing ad conversion instruction to loading complete digital value to register.
LC876596B/80b no.6717-17/23 7. current dissipation characteristics at ta=-30 c to +70 c, vss1=vss2=0v ratings parameter symbol pins conditions vdd[v] min. typ. max unit iddop(1) fmcf=10mhz for ceramic resonator oscillation fsx?tal=32.768khz for crystal oscillation system clock: cf oscillation internal rc oscillation stopped. divider set to 1/1 4.5?6.0 12.5 30.0 iddop(2) cf1=20mhz for external clock fsx?tal=32.768khz for crystal oscillation system clock: cf oscillation internal rc oscillation stopped. divider set to 1/2 4.5?6.0 14.0 31.0 iddop(3) fmcf=4mhz ceramic resonator oscillation fsx?tal=32.768khz for crystal oscillation system clock: cf oscillation internal rc oscillation stopped. divider set to 1/1 4.5?6.0 5.8 17.0 iddop(4) fmcf=0hz (no oscillation) fsx?tal=32.768khz for crystal oscillation system clock: rc oscillation divider set to 1/2 4.5?6.0 1.0 10.0 ma current dissipation during basic operation (note 4) iddop(5) vdd1= vdd2= vdd3= vdd4 fmcf=0hz (no oscillation) fsx?tal=32.768khz for crystal oscillation system clock: 32.768khz internal rc oscillation stopped. divider set to 1/2 4.5?6.0 40 140 a continued/
LC876596B/80b no.6717-18/23 ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iddhalt(1) halt mode fmcf=10mhz for ceramic resonator oscillation fsx?tal=32.768khz for crystal oscillation system clock : cf oscillation internal rc oscillation stopped. divider: 1/1 4.5 to 6.0 5.0 12.0 iddhalt(2) halt mode cf1=20mhz for external clock fsx?tal=32.768khz for crystal oscillation system clock : cf oscillation internal rc oscillation stopped. divider 1/2 4.5 to 6.0 6.0 13.0 iddhalt(3) v dd1= v dd2= v dd3= v dd4 halt mode fmcf=4mhz for ceramic resonator oscillation fsx?tal=32.768khz for crystal oscillation system clock : cf oscillation internal rc oscillation stopped. divider: 1/2 4.5 to 6.0 2.2 6.0 ma iddhalt(4) halt mode fmcf=0hz (when oscillation stops.) fsx?tal=32.768khz for crystal oscillation system clock : rc oscillation divider: 1/2 4.5 to 6.0 500 1600 current dissipation halt mode (note 4) iddhalt(5) halt mode fmcf=0hz (when oscillation stops.) fsx?tal=32.768khz for crystal oscillation system clock : 32.768khz internal rc oscillation stopped. divider: 1/2 4.5 to 6.0 25 100 a continued/
LC876596B/80b no.6717-19/23 ratings parameter symbol pins conditions vdd[v] min. typ. max. unit current dissipation hold mode iddhold(1) vdd1 hold mode cf1=vdd or open circuit (when using external clock) 4.5 to 6.0 0.015 25 current dissipation date/time clock hold mode iddhold(2) vdd1 date/time clock hold mode cf1=vdd or open circuit (when using external clock) fmx?tal=32.768khz for crystal oscillation 4.5 to 6.0 20 90 a (note 4) the currents of the output transistors and the pull-up mos transistors are ignored.
LC876596B/80b no.6717-20/23 main system clock oscillation circuit characteristics the characteristics in the table bellow is based on the following conditions: 1. use the standard evaluation board sanyo has provided. 2. use the peripheral parts with indicated value externally. 3. the peripheral parts value is a recommended value of oscillator manufacturer table 1. main system clock oscillation circuit characteristics using ceramic resonator circuit parameters oscillation stabilizing time frequency manufacturer oscillator c1 c2 rd1 operating supply voltage range typ max notes csa10.0mtz 33pf 33pf 470 ? 4.5-6.0v 0.05ms 0.2ms murata cst10.0mtw (30pf) (30pf) 470 ? 4.5-6.0v 0.05ms 0.2ms built in c1,c2 10mhz kyocera pbrc10.00br-a (10pf) (10pf) 1.0k ? 4.5-6.0v 0.10ms 0.2ms built in c1,c2 csa4.00mg 33pf 33pf 1.5k ? 4.5-6.0v 0.05ms 0.2ms murata cst4.00mgw (30pf) (30pf) 1.5k ? 4.5-6.0v 0.05ms 0.2ms built in c1,c2 4mhz the oscillation stabilizing time is a period until the oscillation becomes stable after vdd becomes higher than minimum operating voltage. (refer to figure4) subsystem clock oscillation circuit characteristics the characteristics in the table bellow is based on the following conditions: 1. use the standard evaluation board sanyo has provided. 2. use the peripheral parts with indicated value externally. 3. the peripheral parts value is a recommended value of oscillator manufacturer table 2. subsystem clock oscillation circuit characteristics using crystal oscillator circuit parameters oscillation stabilizing time frequency manufacturer oscillator c3 c4 rf rd2 operating supply voltage range typ max notes 32.768mhz seiko epson c-002rx 12pf 15pf 10m ? 680k ? 4.5-6.0v 0.8s 2.0s the oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which starts the sub-clock oscillation or after releasing the hold mode. (refer to figure4) (notes) since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. figure 1 ceramic oscillation circuit figure 2 crystal oscillation circuit figure 3 ac timing measurement point c1 c2 cf cf2 cf1 c3 rd2 c4 x?tal xt2 xt1 rf rd1 0.5vdd
LC876596B/80b no.6717-21/23 reset time and oscillation stable time hold release signal and oscillation stable time figure 4 oscillation stablization time power suppl y res internal rc resonator oscillation cf1 , cf2 xt1 , xt2 operation mode reset time tmscf tmsxtal unfixed reset instruction execution mode vdd vdd limit 0v internal rc resonator oscillation cf1,cf2 xt1,xt2 operation mode hold release signal without hold release signal hold release signal valid tmscf tmsxtal hold halt
LC876596B/80b no.6717-22/23 figure 5 reset circuit figure 6 serial input / output test condition (note) set c res , r res values such that reset time exceeds 200 s. c res vdd r res res sioclk datain dataout di0 di1 di2 di3 di4 di5 di6 di7 di8 do0 do1 do2 do3 do4 do5 do6 do7 do8 data ram transmission period (only sio0) sioclk datain dataout tsck tsckl tsckh tsdi thdi tddo sioclk datain dataout tddo tsdi thdi tsckla tsckha data ram transmission period (only sio0)
LC876596B/80b no.6717-23/23 figure 7 pulse input timing condition memo: tpil tpih ps

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